Switching regulators, also referred to as DC to DC converters, are used to generate a constant voltage level on a load using an inductor as a mean of storage of energy and transfer to the load. In operation, switching regulators are often used to convert an input supply voltage to an output voltage at a voltage level appropriate for the internal circuitry of an integrated circuit. For example, a 5 volts supply voltage provided to an integrated circuit may need to be reduced to 2.8 volts on the IC chip to operate the internal circuitry on the chip. A switching regulator provides power supply function through low loss components such as capacitors, inductors, and transformers, and power switches that are turned on and off to transfer energy from the input to the output in packets. A feedback control circuit is used to regulate the energy transfer to maintain a constant output voltage within the desired load limits of the circuit.
A switching regulator can be configured to step up the input voltage or step down the input voltage or both. Specifically, a buck switching regulator, also called a “buck converter,” steps down the input voltage while a boost switching regulator, also called a “boost converter,” steps up the input voltage. A buck-boost switching regulator, or buck-boost converter, provides both step-up and step-down functions.
The operation of the conventional buck switching regulator is well known and is generalized as follows. A conventional buck switching regulator includes a pair of power switches which are turned on and off to regulate an output voltage to be equal to a reference voltage. More specifically, the power switches are alternately turned on and off to generate a switching output voltage at a switching output node, also referred to as the switch node. The switch node is coupled to an LC filter circuit including an output inductor and an output capacitor to generate an output voltage having substantially constant magnitude. The output voltage can then be used to drive a load.
More specifically, the pair of power switches is often referred to as including a “high-side power switch” and a “low-side power switch.” The high-side power switch is turned on to apply energy to the output inductor of the output filter circuit to allow the current through the inductor to build up. When the high-side power switch is turned off, the voltage across the inductor reverses and the current through the inductor reduces during this period. As a result, the inductor current ripples above and below the nominal output current. A relatively constant output voltage is maintained by the output capacitor. The low-side power switch is turned on and off for synchronous rectification operation.
A wide variety of control methods can be applied to switching regulators. One type of switching regulator control scheme is current mode control where the switching regulator modulates the peak current or the valley current in the output inductor in order to deliver the required energy to the load to maintain the desired output voltage. In current mode control, the inductor or power switch current is sensed and the sensed current is compared to a current loop error signal to control the turning on or off of the high-side power switch.
In current mode control switching regulators, the current control loop using peak current mode or valley current mode needs a slope compensation signal added to the sensed current in order to achieve stable operation. The stabilizing effect of the slope compensation signal manifests itself through the slew rate of the slope compensation signal compared with inductor current slew rate, and not through the DC component added. The slope compensation signal can be added using AC coupling (see U.S. Pat. No. 4,837,495) or using DC coupling.
Slope compensation circuit can be provided on-chip, i.e. on the same integrated circuit as the switching regulator, or off-chip, i.e., as discrete components outside of the switching regulator integrated circuit. With the use of on-chip slope compensation, DC coupling of the slope compensation signal is preferred. Furthermore, adaptive slope compensation related to Vin and Vout is preferred as external adjustments are not possible for the on-chip slope compensation circuit.
In most cases, the slope compensation signal needs to be added to at least some of the duty cycle values, if not the entire range of the duty cycle. For example, the slope compensation signal may be added at least for duty cycle (D):D>50% for peak current mode  (1)orD<50% for valley current mode  (2)In the present description, duty cycle D refers to the percentage of time the power switch is turned on relative to the total period of the switching cycle to deliver discrete energy packets or discrete current pulses to the low loss component, such as the inductor, of the switching regulator.
In actual practice, for noise reasons and stability, the slope compensation signal is usually added for D>30-40% for peak current mode and D<60-70% for valley current mode. Also for reasons of adaptability, in a valley current mode control switching regulator, a “proportional slope” compensation adaptive to Vin-Vout is preferred over “fixed slope” compensation.
Adaptive slope compensation using nonlinear relationship between the duty cycle and the slope compensation signal for peak current mode is described in U.S. Pat. Nos. 7,378,822, 6,498,466, 6,611,131, and 6,369,665. Adaptive slope compensation based on sensing Vin, Vout and sizing the slope using linear approximations for the peak current mode control is described in U.S. Pat. No. 4,975,820.
However, the benefits of adding DC slope compensation are accompanied by some problems. In particular, the slope compensation signal added using DC coupling to the sensed current in the inductor generates a DC voltage difference between the programmed current and the sensed current. The DC voltage difference is reflected back on the error amplifier output as an offset voltage. The offset voltage is a function of the input voltage Vin or the output voltage Vout and limits the DC performance of the switching regulators in other ways.
Solutions to the offset problem introduced by using DC slope compensation have been proposed in U.S. Pat. Nos. 6,611,131 and 6,498,466. The solution described in these patents for correcting the DC Offset introduced by the slope compensation signal is to generate a “second slope compensation signal” and adjust the current limit point of the regulator as a function of the second slope compensation signal so as to maintain the current limit to be substantially constant. The “second slope compensation signal” is proportional to the slope compensation signal. Note that this solution adds a transient signal—the second slope compensation signal—to correct the DC offset even in a steady state situation when the input voltage Vin and the output voltage Vout are constant. Other solutions are proposed in U.S. Pat. No. 7,378,822.
For example, U.S. Pat. No. 7,378,822 describes that it is better “to start slope compensation preferably only slightly ahead of PWM switch-OFF” in peak current mode. This example keeps the benefits of the correct slew rate of slope in the moment of decision and reduces dramatically the DC offset introduced by the slope compensation, which is not always present for duty cycle greater than 50%, but only for a much smaller amount of time around the decision point during the period T.
For step down peak current mode control converter, the DC offset introduced by the slope compensation increases with the duty cycle D, and is at the maximum as the converter approaches the dropout point. The step-down peak current mode suffers the disadvantage of the DC offset generated by slope compensation as Vin is lower and closer to dropout, however the DC offset in peak current mode converter is not varying with Vout which is regulated.
For step down valley current mode converter, the DC offset introduced by the slope compensation increases with 1-D, and is at a maximum as the converter approaches the minimum duty cycle. For step down valley current mode converter, in addition to the disadvantage of a large DC offset, the offset is also dependent of (Vin-Vout) which limits the line rejection and limits even the upper range of voltage Vin in the case when the input voltage Vin has a large voltage range.